The present disclosure relates to manufacture of semiconductor devices such as integrated circuits and, more particularly, to methods of inspecting integrated circuits and detecting defects.
Due to continuing technological innovations in the field of semiconductor fabrication, integrated circuit chips are being developed with larger scale of integration and higher device density, as well as lower power consumption and higher operating speeds. In general, integrated circuits are manufactured using FEOL (front-end-of-line) processing technologies to form discrete semiconductor devices within the surface of a silicon wafer followed by BEOL (back-end-of-line) processing techniques to form a multi-level metallurgical interconnection network over the semiconductor devices to provide the wiring and contacts between the semiconductor devices to create the desired circuits. When semiconductor integrated circuits are designed based on sub-micron dimensions and beyond, it is very important that tight dimensional control is achieved since slight variations in processing conditions can generate significant dimensional deviations of the patterned features or other electrical defects. In this regard, semiconductor wafers are typically inspected at various stages/levels of development to ensure quality control and detect and eliminate critical, yield-limiting defects.
Design systematic defects pose critical yield bottlenecks in the semiconductor design process, throughout the yield ramping for a technology. Via opens and shorts are common sources of yield loss. Fortunately opens and shorts can be detected. One of the most effective ways to detect systematic via failure is by electron beam (e-beam) voltage contrast (VC) inspection, which compares the voltage contrast of vias in silicon to the design. Electron beam inspection is a common technique that is employed using an SEM (scanning electron microscope) to detect electrical and physical defects on a semiconductor wafer through VC inspection of a secondary electron image. In general, electron beam VC inspection involves scanning a target region of the wafer with a focused electron beam emitted by an SEM. The electron beam irradiates the target region causing the emission of secondary electrons and a secondary electron detector measures the intensity of the secondary electron emission along the scan path of the electron beam. As a region is scanned, electrons from the electron beam induce surface voltages that vary over the scanned region due to differential charge accumulation of the irradiated features. VC inspection operates on the principle that differences in the induced surface voltages over a scanned region will cause differences in secondary electron emission intensities. For example, for conductive features, electrical defects can be detected as voltage contrast defects due to charging differences between defective structures and non-defective structures.
Such electron beam inspection can effectively detect an open via or a via short using VC in certain logic patterns. The problem is that when opens or shorts are detected, it is not clear if the open or short is at the current via level or at a prior level of the structure.